Home » Uncategorized » Nashville, Haswell Memory System, OpenPOWER, and Chinese Fabs

Nashville, Haswell Memory System, OpenPOWER, and Chinese Fabs

Matt Turner, Business Insider, Pack your bags, Wall Streeters: Your jobs are moving to Nashville, here. Sell the Balance Sheet Simulation Checker into this movement.

UBS has a plan to move about 2,500 jobs to low-cost locations such as Poland, India, China, and Nashville, Tennessee, over the next year.

Yes, Nashville.

The bank announced fourth-quarter results on Tuesday, and in an accompanying presentation it set out examples of cost cuts in the corporate center, which houses things like human resources and IT.

Intel Haswell, Memory Hierarchy Spec sheet, here.

Intel i7-4770 (Haswell), 3.4 GHz (Turbo Boost off), 22 nm. RAM: 32 GB (PC3-12800 cl11 cr2).

L1 Data cache = 32 KB, 64 B/line, 8-WAY.
L1 Instruction cache = 32 KB, 64 B/line, 8-WAY.
L2 cache = 256 KB, 64 B/line, 8-WAY
L3 cache = 8 MB, 64 B/line
L1 Data Cache Latency = 4 cycles for simple access via pointer
L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
L2 Cache Latency = 12 cycles
L3 Cache Latency = 36 cycles
RAM Latency = 36 cycles + 57 ns

Michael Gschwind, Open Power Foundation, Announcing a New Era of Openness with Power 3.0, here.

The Power ISA 3.0 architecture reflects the values of our open ecosystem, enhancing the platform by continuing the evolution of the RISC ISA concepts pioneered by the Power Architecture to deliver high-performance scalable systems optimized around workload needs. The new architecture specification include enhancements such as:

Improved support for string and memory block operations with the vector string facility
Expanded little-endian support
Instruction fusion and PC-relative addressing in support of improved application portability
Hardware garbage collection acceleration
Enhanced in-memory database support
Interrupt and system call enhancements
Hardware support for the native Linux radix page table format

The Economist, Chips on their shoulders, here.

THE Chinese government has been trying, on and off, since the 1970s to build an indigenous semiconductor industry. But its ambitions have never been as high, nor its budgets so big, as they are now. In an earlier big push, in the second half of the 1990s, the government spent less than $1 billion, reckons Morgan Stanley, an American bank. This time, under a grand plan announced in 2014, the government will muster $100 billion-$150 billion in public and private funds.

The aim is to catch up technologically with the world’s leading firms by 2030, in the design, fabrication and packaging of chips of all types, so as to cease being dependent on foreign supplies. In 2015 the government added a further target: within ten years it wants to be producing 70% of the chips consumed by Chinese industry.

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