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Check in with Xeon Phi


Nicole Hemsoth, HPC Wire, Intel Sheds Light on the “Corner to Landing” Leap, here. This seems like a rough system architecture transition for some Wall Street floating point codes. Knights Landing will give you AVX-512 (doubling your SIMD execution throughput) but then pull the clock speed down from 3+ GHz to 1+ GHz (reportedly) in order to give you all the cores to work with. It seems like the latency-sensitive Algorithmic trading folks get hurt the most in this transition since their applications typically need the highest clock frequency as a top priority and then can find ways to use (essentially free) ILP resources on chip. The less latency-sensitive portfolio P&L and Risk codes will have an easier transition to Knights Landing because their applications typically have much simpler load balancing requirements, some like Monte Carlo simulation across the Firm’s derivative contract inventory approaching embarrassingly parallel.

In essence, as we have touched on already, one can look at Knight’s Landing as simply a new Xeon with higher core counts since at least some of the complexities of using it as a coprocessor will no longer be an issue. Unlike with the current Xeon Phi, transfers across PCIe are eliminated, memory is local and Landing acts as a true processor that can carry over the benefits of parallelism and efficiency of Phi in a processor form factor while still offering the option to use it as a coprocessor for specific highly parallel parts of a given workload. So this should make programming for one of these essentially the same as programming for Xeon—that is, in theory.

Despite the emphasis on extending programmability, make no mistake, it’s not as though parallel programming is suddenly going to become magically simple–and certainly that’s still not the case for using coprocessors, says James Reinders, Intel’s software director. However, there are some notable features that will make the transition more seamless.


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