Algo-Logic, HFT Review, Algo-Logic Systems 3rd Generation TCP Endpoint Achieves Ultra-low-latency of 76 -nanoseconds on Stratix V FPGA, here. So, a competitive gateway is under half a mic one way whether you use the proxy or two TCP sessions. 150 nanos for the TCP stack in and out 100 to 200 nanos for the 15c3-5 risk checks. If you trade many tickers over several colo gateways the P&L term in the max capital exposure and duplicate order check typically depend on the number of tickers. You could do this with RDMA to L3 of a commodity microprocessor or execute the risk checks inline on the FPGA. Do all the static stuff inline. If you are running multiple colos you have risk check signals leaving the FPGA anyway so for portfolio level checks I am sort of indifferent to doing them on the FPGA or the x86. Maybe if you are super aggressive, subject to the Algo-Logic constraints, you can drive the one way gateway latency to something like 200 nanos. I like the guys who are doing the price band risk checks in their Algos prior to sending the message to the proxy gateways and just terminating the session if the gateway price band fails to confirm their earlier check. Just wait until the market gaps under some macro stress, that’ll be interesting to see who has their market data servers synchronized. Maybe their plan is to just ditch the market if they see macro gapping and close their open positions manually?
The mature, proven, reliable and network-tested TCP endpoint delivers ultra-low-latency of 76-nanoseconds with the highest possible TCP bandwidth at full duplex rates of 20 Gbps scalable to 40/100 Gbps. Circuits have been implemented on both Altera and Xilinx FPGA devices and are compatible for deployment with all widely deployed FPGA platforms including Terasic DE5Net, Solarflare AOE and NetFPGA 10G. Plans are underway to also certify the IP-Core on additional end-customer platforms, including the Bittware S5PH-Q and Nallatech P385 platforms. The key TCP Endpoint features include:
- 8, 16, 32 TCP Sessions per instance with user-defined MAC, Port, & IP Addresses
- Small Logic Footprint: 6.7% ALMs for 32 TCP sessions in Stratix V A7 for each TOE
- High Throughput: Can send and receive small and large payloads including jumbo frames
- Full 10GE Line Rate (20 Gbps Duplex) in an architecture that scales to support 40GE & 100GE
- Low latency proxy model that allows true parallel processing of client and exchange traffic communicating with a single application session in FPGA logic
- OS independent GUI or UDP network API for control and configuration